Directing communication of data from an image sensor

ABSTRACT

A memory device can be configured to direct communication of data from an image sensor to the memory device and/or image signal processing circuitry coupled thereto. The memory device can be configured to receive first signaling indicative of first data from an image sensor via a first port and provide the first signaling from the memory device to image signal processing (ISP) circuitry via a second port. The memory device can be configured to receiving, by the memory device, second signaling indicative of second data from the image sensor while the ISP circuitry operates on the first data. An image processing operation can be performed using logic circuitry of the memory device. Directing communication of data using the memory device can reduce data transfers, reduce resource consumption of an imaging system, and offload workloads from a host device and/or a host processing device, for example.

TECHNICAL FIELD

The present disclosure relates generally to memory devices, and more particularly, to apparatuses and methods related to directing communication of data from image sensor.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

Memory is also utilized as volatile and non-volatile data storage for a wide range of electronic applications. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged into arrays, with the arrays being used in memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an apparatus in the form of a system in accordance with a number of embodiments of the present disclosure.

FIG. 2 is a schematic diagram of a portion of a memory array in accordance with a number of embodiments of the present disclosure.

FIG. 3 is a block diagram of a system for directing communication of data from an image sensor using a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 4 is a block diagram of a system for directing communication of data from an image sensor using a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 5 is a flow diagram illustrating a method for directing communication of data from an image sensor using a memory device in accordance with a number of embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods related to directing communication of data from image sensor using memory device. In some previous approaches, image signal processing (ISP) circuitry may be employed to operate on data from an image sensor. For example, ISP circuitry may perform preprocessing operations on data from an image sensor. The preprocessed data may then be communicated to a memory device. In such previous approaches, ISP circuitry serves as an intermediary between an image sensor and a memory device to which data from the image sensor is to be stored. Such previous approaches may rely on signaling, from an external source such as a host device, indicative of commands to direct operations performed by ISP circuitry and/or communication of data from an image sensor to ISP circuitry and/or a memory device.

Some previous approaches may include multiple data transfers. As described above, there may be data transfers from an image sensor to ISP circuitry and from the ISP circuitry to a memory array for each set of data output or retrieved from the image sensor. Each data transfer may include multiple operations. For example, a data transfer may include one or more read operations, one or more decompression operations, and/or one or more compression operations. The data transfers, and their associated operations, may increase the consumption of resources (e.g., power, time, etc.) of a system including an image sensor, ISP circuitry, and a memory array (e.g., an imaging system).

In some previous approaches, throughput of data from an image sensor may be limited by intermediary ISP circuitry. Data from the image sensor may be communicated to ISP circuitry for preprocessing. Additional data from the image sensor cannot be communicated to the ISP circuitry until the ISP circuitry outputs the preprocessed data. Thus, the rate at which data can be communicated from an image sensor is constrained by an amount of data that ISP circuitry can operate on concurrently and/or an amount of time needed by the ISP circuitry to process data.

At least one embodiment of the present disclosure addresses shortcomings and other issues associated with some previous approaches, such as the shortcomings and issues described herein, by enabling a memory device to direct communication of a data from an image sensor via a port of the memory device. As used herein, a “port” of a memory device refers to a distinct physical and logical interface of the memory device. Unless indicated otherwise, the terms “port” and “interface” are used interchangeably herein. A port may include multiple physical connections such as pins. Examples of ports include serial ports (e.g., a camera serial interface operated according to a mobile industry processor interface (MIPI) protocol) and memory ports (e.g., a double data rate (DDR) interface). In some embodiments, the memory device is directly coupled to the image sensor via a first port, which can be a serial interface, for example, and the memory device is coupled to ISP circuitry via a second port, which can be a parallel interface. The memory device can have another port for interfacing with a host device. As described herein, at least one embodiment of the present disclosure includes a memory device configured to perform image processing operations on data pulled from an image sensor and/or received by (e.g., written to) the memory device from an image sensor.

At least one embodiment of the present disclosure improves performance of an imaging system because the imaging system includes a memory device being physically closer to an image sensor as compared to some previous approaches. For example, by directly coupling an image sensor to a memory device or reducing the quantity of components on a data path between the image sensor and the memory device, the quantity of data transfers between components of an imaging system are reduced. As used herein, “directly coupled” refers to a connection of two components (e.g., by direct physical contact). Reducing the quantity of data transfers can reduce the resources consumed by or required by an imaging system.

At least one embodiment of the present disclosure improves performance of imaging systems because the memory device does not merely provide storage for data. Rather, the memory device directs communication of data to and from components of an imaging system. The memory device and other components of the imaging system can have a “master-slave” relationship in which the memory device is the master and the other components are slaves. Instead of a component external to the memory device (e.g., a peripheral device) or a component external to the imaging system (e.g., a host device) directing communication of data between components of an imaging system, the memory device directs communication of data between components of the imaging system. This enables data to be retrieved from an image sensor by a memory device coupled thereto while ISP circuitry of the imaging system processes data previously retrieved from the image sensor by the memory device.

To further improve the performance of the imaging system, in at least one embodiment of the present disclosure, the memory device can include logic circuitry configured to perform operations, such as image processing operations, on data written to the memory device. The memory device can perform pre-processing of data retrieved from the image sensor by the memory device prior to communicating the data to ISP circuitry. Performing one or more image processing operations on data prior to communicating the data to ISP circuitry can enable the data to be in a format that is better suited for processing by the ISP circuitry. ISP circuitry can require large amounts of resources (e.g., power, time) to process data. Pre-processing data using the memory device can reduce the quantity of operations performed by the ISP circuitry thereby reducing the resources consumed by the ISP circuitry. Reducing the quantity of operations performed by the ISP circuitry can also reduce the amount of time that the ISP circuitry processes data such that data can be communicated from the ISP circuitry to a peripheral device coupled to the imaging system in less time than some previous approaches.

A memory device can be configured to direct communication of data from an image sensor to the memory device, via a first port of the memory device, and/or ISP circuitry coupled thereto, via second port of the memory device. The memory device can receive data from an image sensor and provide the data to ISP circuitry. The memory device can receive different data from the image sensor while the ISP circuitry operates on data previously received from the image sensor by the memory device. An image processing operation can be performed on data from the image sensor by the memory device using logic circuitry of the memory device. Directing communication of data from an image sensor and to and/or from ISP circuitry using the memory device can reduce data transfers, reduce resource consumption of an imaging system, offload workloads from ISP circuitry, a host device, a host processing device, and/or a peripheral device, for example.

In at least one embodiment of the present disclosure, data transfers from an image sensor to a memory device and/or ISP circuitry can be directed by the memory device. At least one embodiment can enable data to be communicated from an image sensor concurrently with processing of other data previously communicated from the image sensor by ISP circuitry. Performing image processing operations on data from an image sensor, by a memory device, can offload workloads from a host device or a host processing device because, in some previous approaches, a host device or a host processing device may direct pre-processing of data by providing instructions to ISP circuitry, for example. At least one embodiment can reduce resource consumption and/or resource requirements of an imaging system as compared to some previous approaches because fewer data transfers, and operations associated therewith, are needed.

As used herein, the singular forms “a,” “an,” and “the” include singular and plural referents unless the content clearly dictates otherwise. Furthermore, the word “may” is used throughout this application in a permissive sense (i.e., having the potential to, being able to), not in a mandatory sense (i.e., must). The term “include,” and derivations thereof, mean “including, but not limited to.” The term “coupled” means directly or indirectly connected.

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 102 may reference element “102” in FIG. 1, and a similar element may be referenced as 302 in FIG. 3. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention and should not be taken in a limiting sense.

FIG. 1 is a block diagram of an apparatus in the form of a system 100 including a memory device 102 in accordance with a number of embodiments of the present disclosure. As used herein, a memory device 102, a controller 103, a memory array 110, and/or sensing circuitry 106 might also be separately considered an “apparatus.”

The system 100 includes a host device 126, which is labeled as “ISP circuitry,” coupled to the memory device 102, which includes a memory array 110. Examples of the host device 126 include a personal laptop computer, a desktop computer, a digital camera, a smart phone, a memory card reader, or a vehicle (e.g., an autonomous vehicle), among various other types of devices. In some embodiment, the host device 126 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry), but at least includes ISP circuitry as described herein. Hereinafter, the host device 126 is referred to as ISP circuitry 126, without so limiting the host device. The system 100 can include separate integrated circuits or both the ISP circuitry 126 and the memory device 102 can be on the same integrated circuit. As illustrated by FIG. 1, the ISP circuitry 126 is not directly coupled to the image sensor 122. Embodiments of the present disclosure are not limited to the coupling of the image sensor 122 and the ISP circuitry 126 as illustrated by FIG. 1. For example, as described in association with FIG. 4, ISP circuitry can be directly coupled to an image sensor and a memory device can be directly coupled to the ISP circuitry.

For clarity, the system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 110 can be a hybrid memory cube (HMC), computational memory such as a processing-in-memory random access memory (PIMRAM) array, DRAM array, static random access memory (SRAM) array, spin-transfer torque random access memory (STT RAM) array, PCRAM array, thyristor random access memory (TRAM) array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The memory array 110 can comprise memory cells arranged in rows coupled by access lines, which may be referred to herein as word lines or select lines, and columns coupled by digit lines, which may be referred to herein as bit lines, data lines, or sense lines. Although a single memory array 110 is shown in FIG. 1, embodiments are not so limited. For instance, the memory device 102 may include a number of memory arrays 110 (e.g., a number of banks of DRAM cells, NAND flash cells, etc.).

The memory device 102 can include address circuitry 104 to latch address signals for data provided over an input/output “I/O” bus 114 (e.g., data bus and/or address bus) through I/O circuitry 109 (e.g., provided to external ALU circuitry and to DRAM DQs via local I/O lines and global I/O lines). Address signals are received through address circuitry 104 and decoded by a row decoder 105 and a column decoder 107 to access the memory array 110. Data can be read from the memory array 110 by sensing voltage and/or current changes on the digit lines using the sensing circuitry 106. The sensing circuitry 106 can read and latch a page (e.g., row) of data from the memory array 110. The I/O circuitry 109 can be used for bi-directional data communication with the ISP circuitry 126 over the I/O bus 114. In a number of embodiments, sensing circuitry 106 can include a number of sense amplifiers and a respective number of compute components as will be discussed further herein. The write circuitry 108 can be used to write data to the memory array 110.

The controller 103 (e.g., memory controller) decodes signals provided by the control bus 112 from the ISP circuitry 126. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array 110, including data read, data write, and data erase operations. In various embodiments, the controller 103 is responsible for executing instructions from the ISP circuitry 126 and sequencing access to the memory array 110. The controller 103 can be a state machine, sequencer, or some other type of controller, and include hardware and/or firmware (e.g., microcode instructions) in the form of an application specific integrated circuit (ASIC). The controller 103 can control, for example, generation of clock signals and application of the clock signals to a compute component in sensing circuitry in association with shifting data.

As illustrated by FIG. 1, the memory device 102 can be a multi-port memory device. The control bus 112 and the I/O bus 114 can be referred to, collectively, as a port 123 of the memory device 102. FIG. 1 illustrates an image sensor 122 directly coupled to the memory device 102 via port 121 and the ISP circuitry 126 directly coupled to the memory device 102 via port 123. Although the port 121 is illustrated more generically than the port 123, the port 121 can include, for example, a connection to the I/O circuitry 109 or other I/O circuitry (not specifically illustrated).

Although not illustrated by FIG. 1, the memory device 102 can include control circuitry, such as the controller 103, for example, configured to direct communication of data to the memory device 102 and/or from the memory device 102. The control circuitry can be configured to direct communication of data to and/or from the ISP circuitry 126 coupled to the memory device 102. The memory device 102 can direct communication of data from peripheral devices (e.g., the image sensor 122 or another peripheral device (not shown) without communicating the data to and/or from the memory device 102 itself.

The control circuitry can be configured to direct communication of data from the image sensor 122 and/or from the memory device 102 to the ISP circuitry 126. The control circuitry can be configured to direct communication of data from the image sensor 122 to the ISP circuitry 126 without communicating the data to or from the memory device 102. Similarly, the control circuitry can be configured to direct communication of data from the ISP circuitry 126 to another host or peripheral deice without communicating the data to or from the memory device 102. Embodiments of the present disclosure described in association with FIGS. 3 and 4 describe directing communication of data from an image sensor using a memory device in further detail.

In a number of embodiments, the sensing circuitry 106 can be used to perform logical operations using data stored in the memory array 110 as inputs and/or store the results of the logical operations back to the memory array 110 without transferring data via a digit line address access (e.g., without firing a column decode signal). As such, various compute functions can be performed using, and within, the sensing circuitry 106 rather than (or in association with) being performed by processing resources external to the sensing circuitry 106 (e.g., by a processing resource associated with the ISP circuitry 126 and/or other processing circuitry, such as ALU circuitry, located on the memory device 102 (e.g., on the controller 103 or elsewhere)). The sensing circuitry 106 can be configured to perform one or more image processing operations on data written to the memory array 110. Non-limiting examples of image processing operations include a compression operation; a frame buffer operation; an encoding, decoding, or scaling operation; a color space conversion operation; and an attention finding operation.

In various previous approaches, data associated with an operand, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry via I/O lines (e.g., via local I/O lines and/or global I/O lines). The external ALU circuitry could include a number of registers and would perform compute functions using the operands, and the result would be transferred back to the array via the I/O lines. In contrast, in a number of embodiments of the present disclosure, the sensing circuitry 106 is configured to perform logical operations on data stored in the memory array 110 and store the result back to the memory array 110 without enabling an I/O line (e.g., a local I/O line) coupled to the sensing circuitry 106.

As such, in a number of embodiments, circuitry external to the memory array 110 and sensing circuitry 106 is not needed to perform compute functions as the sensing circuitry 106 can perform the appropriate logical operations to perform such compute functions without the use of an external processing resource. Therefore, the sensing circuitry 106 may be used to complement and/or to replace, at least to some extent, such an external processing resource (or at least the bandwidth consumption of such an external processing resource).

However, in a number of embodiments, the sensing circuitry 106 may be used to perform logical operations (e.g., to execute instructions) in addition to logical operations performed by an external processing resource (e.g., the ISP circuitry 126). For instance, the ISP circuitry 126 and/or sensing circuitry 106 may be limited to performing only certain logical operations and/or a certain number of logical operations.

In a number of embodiments, the sensing circuitry 106 can be formed on a same pitch as a pair of complementary sense lines of the array. For example, the cells of a memory array may have a 4F² or 6F² cell size, where “F” is a feature size corresponding to the cells. As an example, a pair of complementary memory cells may have a cell size with a 6F² pitch (e.g., 3F×2F). If the pitch of a pair of complementary sense lines for the complementary memory cells is 3F, then the sensing circuitry being on pitch indicates the sensing circuitry (e.g., a sense amplifier and corresponding compute component per respective pair of complementary sense lines) is formed to fit within the 3F pitch of the complementary sense lines.

Enabling an I/O line can include enabling (e.g., turning on) a transistor having a gate coupled to a decode signal (e.g., a column decode signal) and a source/drain coupled to the I/O line. However, embodiments are not limited to performing logical operations using sensing circuitry (e.g., the sensing circuitry 106) without enabling column decode lines of the memory array 110. Whether or not local I/O lines are used in association with performing logical operations via sensing circuitry 106, the local I/O line(s) may be enabled in order to transfer a result to a suitable location other than back to the memory array 110 (e.g., to an external register).

FIG. 2 is a schematic diagram of a portion of a memory array 210 in accordance with a number of embodiments of the present disclosure. The memory array 210 can be analogous to the memory array 110 described in association with FIG. 1. The memory array 210 can include memory cells 260-1, 260-2, 260-3, 260-4, 260-5, 260-6, 260-7, 260-8, . . . , 260-N coupled to rows of access lines 262-1, 262-2, 262-3, 262-4, 262-5, 262-6, 262-7, . . . , 262-M and columns of sense lines 264-1, 264-2, 264-3, 264-4, 264-5, 264-6, 264-7, 264-8, . . . , 264-N. The memory array 210 is not limited to a particular number of access lines and/or sense lines, and use of the terms “rows” and “columns” does not intend a particular physical structure and/or orientation of the access lines and/or sense lines. Although not illustrated by FIG. 2, each column of memory cells can be associated with a corresponding pair of complementary sense lines.

Each column of memory cells can be coupled to sensing circuitry 206, which can be analogous to the sensing circuitry 106 described in association with FIG. 1. In this example, the sensing circuitry 206 includes a number of sense amplifiers 266-1, 266-2, 266-3, 266-4, 266-5, 266-6, 266-7, 266-8, . . . , 266-N coupled to the respective sense lines 264. The sense amplifiers 266 are coupled to input/output (I/O) line 268 (e.g., a local I/O line) via access devices (e.g., transistors) 270-1, 270-2, 270-3, 270-4, 270-5, 270-6, 270-7, 270-8, . . . , 270-N. In this example, the sensing circuitry also includes a number of compute components 272-1, 272-2, 272-3, 272-4, 272-5, 272-6, 272-7, 272-8, . . . , 272-N coupled to the respective sense lines 264. Column decode lines 274-1, 274-2, 274-3, 274-4, 274-5, 274-6, 274-7, 274-8, . . . , 274-N are coupled to the gates of access devices 270, respectively, and can be selectively activated to transfer data sensed by respective sense amps 266 and/or stored in respective compute components 272 to a secondary sense amplifier 276. In a number of embodiments, the compute components 272 can be formed on pitch with the memory cells of their corresponding columns and/or with the corresponding sense amplifiers 266.

In a number of embodiments, the sensing circuitry (e.g., compute components 272 and sense amplifiers 266) is configured to perform a number of logical operations on elements stored in the memory array 210. As an example, a first plurality of elements can be stored in a first group of memory cells coupled to a particular access line (e.g., access line 262-1) and to a number of sense lines 264, and a second plurality of elements can be stored in a second group of memory cells coupled to a different access line (e.g., access line 262-2) and the respective number of sense lines 264. Each element of the first plurality of elements can have a logical operation performed thereon with a respective one of the second plurality of elements, and the result of the logical operation can be stored (e.g., as a bit-vector) in a third group of memory cells coupled to a particular access line (e.g., access line 262-3) and to the number of sense lines 264.

FIG. 3 is a block diagram of a system 330 for directing communication from an image sensor 322 using a memory device 302 in accordance with the present disclosure. Each of the components of the system 330 can be on a separate chip. However, the system 330 can be a stack of chips. The image sensor 322 can be directly coupled to the memory device 302. The memory device 302 can be directly coupled to ISP circuitry 326.

In contrast to some previous approaches, the image sensor 322 is not directly coupled to the ISP circuitry 326. For example, in contrast to some previous approaches, the memory device 302 does not include through-silicon vias (TSVs) so that the image sensor 322 is coupled to the ISP circuitry 326. In contrast to some previous approaches, the memory device 302 can be configured to ingest data directly from the image sensor 322 rather than the ISP circuitry 326.

Although not illustrated by FIG. 3, the memory device 302 can include control circuitry, such as the controller 103 described in association with FIG. 1, configured to direct communication of signaling indicative of data from the image sensor 322 to the memory device 302. The control circuitry can be configured to direct communication of signaling indicative of data from the memory device 302 to the ISP circuitry 326. The control circuitry can be configured to direct communication of signaling indicative of data from the ISP circuitry 326 to a different device (not shown).

The memory device 302 can be configured to direct writing of data directly from the image sensor 322 to the memory device 302. The memory device 302 can be configured to direct performance of an image processing operation on data written to the memory device 302. The memory device 302 can be configured to direct communication of operated-on data (data on which the image processing operation was performed) from the memory device 302 to the ISP circuitry 326 concurrently with writing of data directly from the image sensor 322 to the memory device 302.

In at least one embodiment, the port 321 between the image sensor 322 and the memory device 302 can be a serial interface. The port 321 is a port of the memory device 302. A serial interface between the image sensor 322 and the memory device 302 can reduce the quantity of pins needed to couple the memory device 302 to the image sensor 322. Thus, the port 321 occupies a smaller space on the memory device 302. In at least one embodiment, port 323 between the memory device 302 and the ISP circuitry 326 can be a parallel interface. A parallel interface provides an increased data rate because more data can be communicated from the memory device 302 to the ISP circuitry 326 concurrently.

At least one embodiment can include the port 321 being a serial interface and the port 323 being a parallel interface. These embodiments can provide a low pin-count between the image sensor 322 and the memory device 302 while still providing the bandwidth of a parallel interface between the memory device 302 and the ISP circuitry 326 for accessing the memory device 302.

As illustrated by FIG. 3, the system 330 includes a serializer 328 coupled to the memory device via port 335. The port 335 can be a parallel interface which is converted to a serial interface by the serializer 328. The serializer 328 can be configured to communicate data from the ISP circuitry 326 to a component external to the system 330 (not shown). Examples of components external to the system 330 include, but are not limited to, a host device and a host processing device. A host device and/or a host processing device can be a component of a vehicle (e.g., an autonomous vehicle). Although FIG. 3 illustrates the serializer 328 as a separate component, in at least one embodiment the serializer 328 can be a component of the ISP circuitry 326.

The memory device 302 can include an array of memory cells, such as the memory array 110 described in association with FIG. 1. The memory device 302 can be configured to receive (e.g., retrieve and/or pull) data from the image sensor 322. The memory device 302 can be configured to retrieve and/or 3 pull data directly from the image sensor 322. Data from the image sensor 322 can be written to the memory device 302. For example, data retrieved and/or pulled from the image sensor 322 can be written to an array of memory cells of the memory device 302. The memory device 302 can be configured to map addresses of memory cells of an array of memory cells to which data from the image sensor 322 is written to columns and rows of a corresponding image array captured by the image sensor 322. The memory device 302 can map individual portions of an image array to individual memory cells to which data corresponding to those individual portions of the image array were written.

The memory device 302 can include logic circuitry 327. The logic circuitry 327 can be coupled to an array of memory cells of the memory device 302. The logic circuitry 327 is configured to perform one or more operations on data written to the memory device 302. For example, the logic circuitry 327 can be configured to perform one or more image processing operations on data from the image sensor 322 written to the memory device 302. Non-limiting examples of image processing operations include a compression operation; a frame buffer operation; an encoding, decoding, or scaling operation; a color space conversion operation (e.g., an artificial intelligence (AI) color space conversion); and an attention finding operation. The logic circuitry 327 can be configured to perform one or more logical operations to perform one or more image processing operations. In at least one embodiment, the logic circuitry 327 can be a component of sensing circuitry of the memory device 302, such as the sensing circuitry 106 described in association with FIG. 1. In at least one embodiment, the logic circuitry 327 can be an ASIC separate from the sensing circuitry.

The control circuitry can be configured to direct performance of an operation, such as an imaging processing operation, by the logic circuitry 327 on data pulled from the image sensor 322 by the memory device 302 and/or data written to the memory device 302. Performing an image processing operation on data from the image sensor 322 prior to communicating the data to the ISP circuitry 326 can provide the data in a better format for processing by the ISP circuitry 326.

The system 330 can be a component of a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, an Internet-of-Things (IoT) enabled device, or a vehicle (e.g., an autonomous vehicle), among various other types of systems. For clarity, the system 330 has been simplified to focus on features with particular relevance to the present disclosure. The system 330 can be a component of an event recorder of a vehicle, such as an autonomous vehicle. An event recorder may also be referred to as a black box.

The memory device 302 can provide main memory for the system 330 or could be used as additional memory or storage throughout the system 330. By way of example, the memory device 302 can be a dual in-line memory module (DIMM) operated as DDR DRAM, such as DDR5, a graphics DDR DRAM, such as GDDR6, or another type of memory system. Embodiments are not limited to a particular type of memory device 302. Other examples can include RAM, ROM, SDRAM, PCRAM, RRAM, flash memory, and three-dimensional cross-point, among others. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased.

Although not illustrated by FIG. 3, the memory device 302 can include a state machine. For example, the control circuitry can include a state machine. The state machine can be configured to count clock cycles of the image sensor 322 so that the memory device 302 can direct retrieval of data from the image sensor 322. The memory device 302 or the control circuitry can be configured to synchronize signaling indicative of a clock of the memory device 302 with signaling indicative of a clock of the image sensor 322.

Although not illustrated in FIG. 3, the memory device 322 can include registers configured to maintain pointers to start locations and stop locations of the memory device 302 at which data from the image sensor 322 is written. For example, a pointer to a start location can be indicative of a row and/or column of an array of memory cells of the memory device 302 (e.g., an address of the memory device 302) at which writing of data from the image sensor 322 started. A pointer to a stop location can be indicative of a row and/or column of an array of memory cells of the memory device 302 at which writing of data from the image sensor 322 stopped. The registers can be in a data path between a data port of the memory device 302 coupled to the image sensor 322 and a memory cell of the memory device 302.

FIG. 4 is a block diagram of a system 440 for directing communication of data from an image sensor 422 using a memory device 402 in accordance with the present disclosure. The image sensor 422, the memory device 402, the ISP circuitry 426, the serializer 428, and the logic circuitry 427 can be analogous to the image sensor 322, the memory 302, the ISP circuitry 326, the serializer 328, and the logic circuitry 327 described in association with FIG. 3. The system 440 differs from the system 330 in that the coupling between the image sensor 422 and the memory device 402, ISP circuitry 426, and serializer 428 is different.

In the system 440, the image sensor 422 is directly coupled to the ISP circuitry 426 rather than being directly coupled to the memory device 402. The connections between the memory device 402 and the ISP circuitry 426 (port 423) and between the memory device 402 and the serializer 428 (port 435) are analogous to those illustrated and described with respect to FIG. 3; however, the data pipeline is different.

Although the memory device 402 is not directly coupled to the image sensor 422, the memory device 402 is configured to direct communication of data from the image sensor 422 to the ISP circuitry 426. The memory device 402 is configured to direct communication of data from the ISP circuitry 426 to the memory device 402 via the first port of the memory device 402 (port 423). The memory device 402 is configured to direct communication of data from the memory device 402 to the ISP circuitry 426 via the first port of the memory device 402 (port 423). The memory device 402 is configured to direct communication of data from the memory device 402 to the serializer 428 via the second port of the memory device 402 (the port 435). The memory device 402 is configured to direct communication of data from the serializer 428 to a component external to the system 440. For example, the memory device 402 can be configured to transfer data from the image sensor 422 to the ISP circuitry 426. The memory device 402 can be configured to transfer data from the ISP circuitry 426 to the serializer 428. The memory device 402 can be configured to transfer data from the serializer 428 to a host device.

As described in association with FIGS. 1 and 3, the memory device 402 can be configured to perform operations, such as image processing operations, on data pulled from the image sensor 422 by the memory device 402. Although the system 440 includes the ISP circuitry 426 being in the data path between the image sensor 422 and the memory device 402, the system 440 still enables the memory device 402 to perform operations on data retrieved from the image sensor 402. For example, the memory device 402 can be configured to perform one or more image processing operations on data retrieved from the image sensor 422 prior to the ISP circuitry 422 processes the data. The memory device 402 can be configured to perform one or more image processing operations on data retrieved from the image sensor 422 after the data has been processed by the ISP circuitry 426. Performing image processing operations on data before or after the data is processed by the ISP circuitry 426 can offload workloads from the ISP circuitry 426.

FIG. 5 is a flow diagram illustrating a method for direct communication from an image sensor to a memory device in accordance with the present disclosure. The method described in association with FIG. 5 can be performed by, for example, the memory device 102 described in association with FIG. 1.

At block 550, the method can include receiving, by a memory device and via a first port of the memory device, signaling indicative of first data from an image sensor. At block 552, the method can include providing the first signaling indicative of the first data from the memory device to ISP circuitry via a second port of the memory device. At block 554, the method can include receiving, by the memory device and via the first port, second signaling indicative of second data from the image sensor while the ISP circuitry operates on the first data.

Although not illustrated by FIG. 5, the method can include writing the second data to an array of memory cells of the memory device while the ISP circuitry operates on the first data. An image processing operation can be performed on the second data using logic circuitry of the memory device. Subsequently, third signaling indicative of the operated-on second data can be provided to the ISP circuitry via the second port of the memory device. The method can include communicating third signaling indicative of processed data from the ISP circuitry, via the second port of the memory device, to a peripheral device. Communication of the first signaling and the second signaling from the image sensor to the memory device, via the first port of the memory device, can be directed by the memory device without interaction with a host device. Communication of the first signaling from the memory device to the ISP circuitry, via the first port of the memory device, can be directed by the memory device without interaction with the host device.

Embodiments can include a tangible machine-readable storage medium (also known as a computer-readable medium) on which is stored one or more sets of instructions or software embodying any one or more of the methodologies or functions described herein. In some embodiments, a memory device or a processing device constitutes a machine-readable medium. The term “machine-readable storage medium” includes a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” includes any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” includes, but is not be limited to, solid-state memories, optical media, and magnetic media.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. 

What is claimed is:
 1. A method, comprising: receiving, by a memory device and via a first port of the memory device, first signaling indicative of first data from an image sensor; providing, by the memory device and via a second port of the memory device, the first signaling from the memory device to image signal processing (ISP) circuitry; and receiving, by the memory device and via the first port, second signaling indicative of second data from the image sensor while the ISP circuitry operates on the first data.
 2. The method of claim 1, further comprising writing the second data to an array of memory cells of the memory device while the ISP circuitry operates on the first data.
 3. The method of claim 1, further comprising: performing an image processing operation on the second data using logic circuitry of the memory device; and subsequently providing third signaling indicative of the operated-on second data to the ISP circuitry via the second port of the memory device.
 4. The method of claim 1, further comprising communicating third signaling indicative of processed data from the ISP circuitry to a peripheral device.
 5. The method of claim 1, further comprising directing, by the memory device, communication of the first signaling and the second signaling from the image sensor to the memory device via the first port of the memory device.
 6. The method of claim 1, further comprising directing, by the memory device, communication of the first signaling from the memory device to the ISP circuitry via the second port of the memory device.
 7. A memory device, comprising: an array of memory cells; a first port; a second port; and control circuitry configured to direct communication of: first signaling indicative of data from an image sensor to the array of memory cells via the first port; and second signaling indicative of data from the array of memory cells to image signal processing (ISP) circuitry via the second port.
 8. The memory device of claim 7, wherein the control circuitry is further configured to direct communication of third signaling indicative of data from the ISP circuitry to a peripheral device.
 9. The memory device of claim 7, further comprising logic circuitry coupled to the array of memory cells and configured to perform an operation on data pulled from the image sensor and written to the array of memory cells; and wherein the control circuitry is further configured to direct communication third signaling indicative of operated-on data from the logic circuitry to the ISP circuitry.
 10. The memory device of claim 9, wherein the logic circuitry is configured to perform an image processing operation on the pulled data.
 11. The memory device of claim 10, wherein the image processing operation comprises at least one of: a compression operation; a frame buffer operation; an encoding, decoding, or scaling operation; a color space conversion operation; and an attention finding operation.
 12. The memory device of claim 7, wherein the first port comprises a serial interface configured to receive the first signaling.
 13. The memory device of claim 12, wherein the second port comprises a parallel interface configured to communicate the second signaling.
 14. The memory device of claim 7, wherein the control circuitry is further configured to synchronize signaling indicative of a clock of the memory device with signaling indicative of a clock of the image sensor.
 15. The memory device of claim 7, wherein the control circuitry is further configured to map addresses of memory cells of the array to which the data is written, to columns and rows of a corresponding image array captured by the image sensor.
 16. A system, comprising: an image sensor; image signal processing (ISP) circuitry; and a memory device coupled to the image sensor via a serial interface and the ISP circuitry via a parallel interface, wherein the memory device comprises: an array of memory cells; a first port; a second port; and control circuitry configured to direct: writing of data directly from the image sensor to the array of memory cells via the first port; performance of an image processing operation on the data written to the array of memory cells; and communication of signaling indicative of operated-on data from the memory device to the ISP circuitry, via the second port, concurrently with writing of data directly from the image sensor to the array of memory cells.
 17. The system of claim 16, further comprising a serializer coupled to the memory device via a third port of the memory device, wherein the memory device is coupled between the ISP circuitry and the serializer.
 18. The system of claim 17, wherein the control circuitry is further configured to direct communication of signaling indicative of data from the ISP circuitry to a peripheral device.
 19. The system of claim 16, wherein the memory device comprises dynamic random-access memory (DRAM).
 20. The system of claim 16, wherein the memory device further comprises a plurality of registers, and wherein the circuitry is further configured to maintain pointers to start locations and stop locations of the array of memory cells to which data from the image sensor is written.
 21. The system of claim 16, wherein the control circuitry comprises a state machine. 